The present invention generally relates to communication systems, and, more particularly, to a radio frequency (RF) transceiver for a cellular communication system.
Cellular communication systems includes a mobile switching center (MSC), home location registers (HLR), base station controllers (BSC), base transceiver stations (BTS), and user equipment (UE). A BTS facilitates communication between the UEs and an MSC over a cellular network. The BTS includes an RF transceiver for transmitting and receiving RF signals to and from the UEs. Terms such as MSC, BSC, BTS, and UE are technology standard specific, and in this case are used in context of the Global System for Mobile communication (GSM) standard of wireless communication. For instance, the term BTS in the GSM standard corresponds to Node-B in the third generation (3G) and eNode-B in the fourth generation (4G) standards. The RF transceiver modulates a carrier wave by changing one or more characteristics of the carrier wave, viz. amplitude, frequency, and phase, based on an RF signal. The RF transceiver transmits a modulated carrier wave on a transmission medium using an antenna.
FIG. 1 illustrates a conventional RF transceiver system 100 that includes a conventional RF transceiver 102 that is connected to an antenna 104 for transmitting the modulated carrier wave (hereinafter referred to as a “high-power RF signal”).
The RF transceiver 102 includes a baseband processing unit 106, an RF integrated circuit (RFIC) 108, and a power amplifier (PA) 110. The baseband processing unit 106 includes a digital signal processor (DSP) 112, a system bus 114, a digital pre-distorter (DPD) 116, a direct memory access system (DMA) 118, a system memory 120, an event control module 122, and an antenna interface 124. The RFIC 108 includes an antenna interface 126, a data converter 128, and an RF mixer 130. The data converter 128 includes a digital-to-analog converter (DAC) 132 and an analog-to-digital converter (ADC) 134.
The DSP 112 performs logical and mathematical operations on digital data such as audio and video data and generates digital samples. The DSP 112 is connected to the DPD 116, the DMA 118, and the system memory 120 via the system bus 114. The event control module 122 is connected to the DSP 112 and generates trigger signals to control the timing of events in the baseband processing unit 106 and the RFIC 108. The DSP 112 controls the event control module 122 by providing control trigger signals to the event control module 122. The DSP 112 generates input signals based on the digital samples and provides the input signals to the DPD 116. The antenna 104 may include multiple antennas. The DSP 112 generates input signals corresponding to the antennas 104.
The DPD 116 receives the input signals and generates pre-distorted output signals by multiplying the input signals with corresponding sets of coefficients from lookup tables (LUTs) (not shown) stored therein. The sets of coefficients are referred to as LUT coefficients. The system memory 120 stores digital data corresponding to the pre-distorted output signals.
The DMA 118 and the DPD 116 are connected to the data converter 128 via the antenna interfaces 124 and 126. The antenna interface 124 receives the pre-distorted output signals from the DPD 116 and transfers the pre-distorted output signals to the antenna interface 126. The DAC 132 receives the pre-distorted output signals from the antenna interface 126 and generates baseband signals. The RF mixer 130 that is connected to the DAC 132 receives the baseband signals and generates analog RF signals.
The PA 110 that is connected to the RF mixer 130 receives the analog RF signals and generates amplified analog RF signals. The PA 110 may include, for example, multiple PAs corresponding to the antennas 104, where a PA amplifies a corresponding analog RF signal and provides the amplified RF signal to the antennas 104.
The RF mixer 130 receives the amplified analog RF signals from the PA 110 as a feedback and generates analog feedback signals. The ADC 134 receives the analog feedback signals and generates digital feedback signals. The DMA system 118 receives digital data corresponding to the digital feedback signals by way of the antenna interfaces 126 and 124, and stores the digital feedback signals in the system memory 120.
The DSP 112 accesses the system memory 120 and compares the digital feedback signals with the pre-distorted output signals. The DSP 112 selects alternate LUT coefficients from the LUT in the DPD 116 based on the comparison of the digital feedback signals with the pre-distorted output signals. In another example, the DSP 112 updates the LUT coefficients of the LUT in the DPD 116 based on the comparison of the digital feedback signals with the pre-distorted output signals.
It is desirable that the PA 110 achieves high efficiency and linearity. For instance, class A PAs are linear PAs but are very expensive and unsuitable for cellular communication systems. Hence, less expensive and non-linear PAs such as class AB, B, and C PAs are widely used.
To maintain linearity of the PAs, digital pre-distortion technique is used. The DPD 116 performs a mathematical inversion of the digital feedback signals received from the PA 110 by way of the ADC 134. The DPD 116 is a non-linear module and the LUT coefficients have inverse characteristic of the digital feedback signals. Thus, the pre-distorted output signals generated by the DPD 116 have an inverse characteristic of the digital feedback signals. When the non-linear PA 110 receives the pre-distorted output signals from the non-linear DPD 116, the PA 110 generates a linear amplified analog RF signal. The aforementioned technique is referred to as digital pre-distortion.
In another example, the DPD 116 uses a dynamic deviation reduction-based Volterra model. The DPD 116 includes a parameter extraction unit (not shown), that receives the digital feedback signal and updates the LUT coefficients based on a Volterra model. The dynamic deviation reduction-based Volterra model is widely used to model the non-linearity of the PAs with memory effects.
FIG. 2 illustrates a schematic block diagram of the DPD 116 of the conventional RF transceiver system 100 of FIG. 1. The DPD 116 is connected to the RFIC 108, and receives the input signals corresponding to the antennas 104 from the DSP 112 and outputs the pre-distorted output signals corresponding to the antennas 104. The DPD 116 includes multiple DPD processing chains corresponding to the antennas 104. A DPD processing chain includes components such as an address generator, a set of LUTs, a set of multipliers, and an adder.
For example, the antennas 104 may include first and second antennas 202a and 202b, so the DPD 116 would include first and second DPD processing chains. The first DPD processing chain includes a first address generator 204a, a first set of LUTs 206a, a first set of multipliers 208a, and a first adder 210a. The first address generator 204a receives a first input signal and generates a first set of addresses.
The first set of LUTs 206a includes multiple LUTs that store multiple LUT coefficients. The first set of LUTs 206a receives the first set of addresses and outputs a first set of LUT coefficients. The first set of multipliers 208a receives the first input signal and the first set of LUT coefficients and generates a first set of pre-distorted digital samples. The first adder 210a receives and accumulates the first set of pre-distorted digital samples and generates a first pre-distorted output signal. The DPD 116 provides the first pre-distorted output signal to the first antenna 202a by way of a first DAC 212a and a first power amplifier 214a. 
Similarly, the second DPD processing chain includes a second address generator 204b, a second set of LUTs 206b, a second set of multipliers 208b, and a second adder 210b that are structurally and functionally similar to the first address generator 204a, the first set of LUTs 206a, the first set of multipliers 208a, and the first adder 210a, respectively. The DPD 116 generates and provides a second pre-distorted output signal to the second antenna 202b by way of a second DAC 212b and a second power amplifier 214b. 
Thus, for each antenna 104, the DPD 116 includes a set of LUTs and a set of multipliers and hence, for multiple antennas, the DPD 116 includes multiple sets of LUTs and multipliers, thereby increasing the area, complexity and cost of implementation of the DPD 116.
Generally, the RF transceiver 102 is designed to support different types of PAs 110. Each PA 110 has distinct characteristics such as linearity and efficiency. In some cases, the RF transceiver 102 is required to support different antenna configurations and different bandwidths. For instance, the RF transceiver 102 may be required to support a 4×4 multiple-input and multiple-output (MIMO) configuration with a bandwidth of 20 MHz. The RF transceiver 102 may also be required to support a 2×2 MIMO configuration with a bandwidth of 40 MHz. However, the connections between the components of the DPD processing chain within the DPD 116 are fixed, and hence, the conventional DPD 116 cannot be used for the RF transceiver 102 having different configurations. Thus, there is a need for a DPD that has reduced area and complexity and supports different configurations of bandwidth, antenna count, and type of PA.
A known technique to overcome the aforementioned problems is to use high-speed digital hardware circuits such as field-programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs) to implement the DPD. However, FPGAs and ASICs are expensive and hence, not feasible for low-cost implementation of DPD.
Another known technique to overcome the aforementioned problem uses a common multiplier shared between the set of LUTs for an antenna. The set of LUTs includes coefficients from a truncated Volterra series of the Volterra model and is utilized for an LUT assisted gain indexing. The shared multiplier is time-division multiplexed for sharing between the set of LUTs. Thus, for each antenna, a single shared multiplier is used. However, multiple multipliers are required for RF transceivers catering to multiple antennas. Therefore, the presence of multiple multipliers and LUTs increases the cost and area of an RF transceiver that includes the aforementioned system. Further, the aforementioned system does not cater to different configurations of the RF transceiver, such as varying bandwidth of the antennas and non-linearity of the PAs.
Therefore, it would be advantageous to have a digital pre-distorter (DPD) that supports different configurations of a RF transceiver having different bandwidths, antenna count and power amplifiers, has reduced area and complexity, and reduced implementation cost.